/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * The NAU83G10/20 Boosted Mono Class-D Amplifier with DSP and I/V-sense driver.
 *
 * Copyright 2021 Nuvoton Technology Crop.
 * Author: John Hsu <KCHSU0@nuvoton.com>
 *         David Lin <ctlin0@nuvoton.com>
 */

#ifndef __NAU8310_H__
#define __NAU8310_H__

#define NAU8310_R00_HARDWARE_RST		0x00
#define NAU8310_R01_SOFTWARE_RST		0x01
#define NAU8310_R02_I2C_ADDR			0x02
#define NAU8310_R03_CLK_CTRL			0x03
#define NAU8310_R04_ENA_CTRL			0x04
#define NAU8310_R05_INTERRUPT_CTRL		0x05
#define NAU8310_R06_INT_CLR_STATUS		0x06
#define NAU8310_R07_SAR_CTRL1			0x07
#define NAU8310_R08_GPIO124_CTRL		0x08
#define NAU8310_R09_GPIOOUT			0x09
#define NAU8310_R0A_IO_CTRL			0x0a
#define NAU8310_R0B_I2S_PCM_CTRL0		0x0b
#define NAU8310_R0C_TDM_CTRL			0x0c
#define NAU8310_R0D_I2S_PCM_CTRL1		0x0d
#define NAU8310_R0E_I2S_PCM_CTRL2		0x0e
#define NAU8310_R0F_LEFT_TIME_SLOT		0x0f
#define NAU8310_R10_RIGHT_TIME_SLOT		0x10
#define NAU8310_R12_HPF_CTRL			0x12
#define NAU8310_R13_MUTE_CTRL			0x13
#define NAU8310_R14_ADC_VOL_CTRL		0x14
#define NAU8310_R15_INT_COE			0x15
#define NAU8310_R16_DEC_COE			0x16
#define NAU8310_R17_BOOST_CTRL1			0x17
#define NAU8310_R18_BOOST_CTRL2			0x18
#define NAU8310_R19_DSP_CORE_CTRL1		0x19
#define NAU8310_R1A_DSP_CORE_CTRL2		0x1a
#define NAU8310_R1B_CLK_DOUBLER_O		0x1b
#define NAU8310_R1C_BOOST_CTRL_O		0x1c
#define NAU8310_R1D_GENERAL_STATUS0		0x1d
#define NAU8310_R1E_GENERAL_STATUS1		0x1e
#define NAU8310_R1F_GENERAL_STATUS2		0x1f
#define NAU8310_R20_SAR_ADC_OUT_01		0x20
#define NAU8310_R21_SAR_ADC_OUT_23		0x21
#define NAU8310_R22_ALC_READOUT1		0x22
#define NAU8310_R23_ALC_READOUT2		0x23
#define NAU8310_R24_ALC_READOUT3		0x24
#define NAU8310_R25_DSP_STATUS_0		0x25
#define NAU8310_R26_DSP_STATUS_1		0x26
#define NAU8310_R27_DSP_STATUS_2		0x27
#define NAU8310_R28_ADC_RATE			0x28
#define NAU8310_R29_DAC_CTRL1			0x29
#define NAU8310_R2A_DAC_CTRL2			0x2a
#define NAU8310_R2C_ALC_CTRL1			0x2c
#define NAU8310_R2D_ALC_CTRL2			0x2d
#define NAU8310_R2E_ALC_CTRL3			0x2e
#define NAU8310_R2F_ALC_CTRL4			0x2f
#define NAU8310_R30_TEMP_COMP_CTRL		0x30
#define NAU8310_R31_UVLO_CTRL0			0x31
#define NAU8310_R32_UVLO_CTRL1			0x32
#define NAU8310_R33_LPF_CTRL			0x33
#define NAU8310_R40_CLK_DET_CTRL		0x40
#define NAU8310_R46_I2C_DEVICE_ID		0x46
#define NAU8310_R49_SARDOUT_RAM_STATUS		0x49
#define NAU8310_R4A_ANALOG_READ			0x4a
#define NAU8310_R55_MISC_CTRL			0x55
#define NAU8310_R60_BIAS_ADJ			0x60
#define NAU8310_R61_ANALOG_CONTROL_1		0x61
#define NAU8310_R62_ANALOG_CONTROL_2		0x62
#define NAU8310_R63_ANALOG_CONTROL_3		0x63
#define NAU8310_R64_ANALOG_CONTROL_4		0x64
#define NAU8310_R65_ANALOG_CONTROL_5		0x65
#define NAU8310_R66_ANALOG_CONTROL_6		0x66
#define NAU8310_R68_ANALOG_CONTROL_7		0x68
#define NAU8310_R69_CLIP_CTRL			0x69
#define NAU8310_R6B_ANALOG_CONTROL_8		0x6b
#define NAU8310_R6C_ANALOG_CONTROL_9		0x6c
#define NAU8310_R71_ANALOG_ADC_1		0x71
#define NAU8310_R72_ANALOG_ADC_2		0x72
#define NAU8310_R73_RDAC			0x73
#define NAU8310_R76_BOOST			0x76
#define NAU8310_R77_FEPGA			0x77
#define NAU8310_R7F_POWER_UP_CONTROL		0x7f
#define NAU8310_R80_BIQ0_COE_1			0x80
#define NAU8310_R81_BIQ0_COE_2			0x81
#define NAU8310_R82_BIQ0_COE_3			0x82
#define NAU8310_R83_BIQ0_COE_4			0x83
#define NAU8310_R84_BIQ0_COE_5			0x84
#define NAU8310_R85_BIQ0_COE_6			0x85
#define NAU8310_R86_BIQ0_COE_7			0x86
#define NAU8310_R87_BIQ0_COE_8			0x87
#define NAU8310_R88_BIQ0_COE_9			0x88
#define NAU8310_R89_BIQ0_COE_10			0x89
#define NAU8310_R8A_BIQ1_COE_1			0x8a
#define NAU8310_R8B_BIQ1_COE_2			0x8b
#define NAU8310_R8C_BIQ1_COE_3			0x8c
#define NAU8310_R8D_BIQ1_COE_4			0x8d
#define NAU8310_R8E_BIQ1_COE_5			0x8e
#define NAU8310_R8F_BIQ1_COE_6			0x8f
#define NAU8310_R90_BIQ1_COE_7			0x90
#define NAU8310_R91_BIQ1_COE_8			0x91
#define NAU8310_R92_BIQ1_COE_9			0x92
#define NAU8310_R93_BIQ1_COE_10			0x93
#define NAU8310_R94_BIQ2_COE_1			0x94
#define NAU8310_R95_BIQ2_COE_2			0x95
#define NAU8310_R96_BIQ2_COE_3			0x96
#define NAU8310_R97_BIQ2_COE_4			0x97
#define NAU8310_R98_BIQ2_COE_5			0x98
#define NAU8310_R99_BIQ2_COE_6			0x99
#define NAU8310_R9A_BIQ2_COE_7			0x9a
#define NAU8310_R9B_BIQ2_COE_8			0x9b
#define NAU8310_R9C_BIQ2_COE_9			0x9c
#define NAU8310_R9D_BIQ2_COE_10			0x9d
#define NAU8310_RF000_DSP_COMM			0xf000
#define NAU8310_REG_MAX				NAU8310_RF000_DSP_COMM
/* 16-bit control register address, and 16-bits control register data */
#define NAU8310_REG_ADDR_LEN			16
#define NAU8310_REG_DATA_LEN			16


/* CLK_CTRL (0x03) */
#define NAU8310_CLK_ADC_DIV2_SFT		12
#define NAU8310_CLK_ADC_DIV2			(0x1 << NAU8310_CLK_ADC_DIV2_SFT)
#define NAU8310_CLK_ADC_DIV4_SFT		11
#define NAU8310_CLK_ADC_DIV4			(0x1 << NAU8310_CLK_ADC_DIV4_SFT)
#define NAU8310_CLK_ADC_SRC_SFT			6
#define NAU8310_CLK_ADC_SRC_MASK		(0x3 << NAU8310_CLK_ADC_SRC_SFT)
#define NAU8310_CLK_DAC_SRC_SFT			4
#define NAU8310_CLK_DAC_SRC_MASK		(0x3 << NAU8310_CLK_DAC_SRC_SFT)
#define NAU8310_MCLK_SRC_MASK			0x7

/* ENA_CTRL (0x04) */
#define NAU8310_DSP_OSC_SFT			14
#define NAU8310_DSP_OSC_EN			(0x1 << NAU8310_DSP_OSC_SFT)
#define NAU8310_DSP_SEL_OSC_SFT			13
#define NAU8310_DSP_SEL_OSC			(0x1 << NAU8310_DSP_SEL_OSC_SFT)
#define NAU8310_MCLK_SEL_SFT			8
#define NAU8310_MCLK_SEL_MASK			(0x7 << NAU8310_MCLK_SEL_SFT)
#define NAU8310_CLK_MUL_SRC_SFT			6
#define NAU8310_CLK_MUL_SRC_MASK		(0x3 << NAU8310_CLK_MUL_SRC_SFT)
#define NAU8310_CLK_DSP_SRC_SFT			3
#define NAU8310_CLK_DSP_SRC_MASK		(0x7 << NAU8310_CLK_DSP_SRC_SFT)
#define NAU8310_DAC_CH_EN_SFT			2
#define NAU8310_DAC_CH_EN			(0x1 << NAU8310_DAC_CH_EN_SFT)
#define NAU8310_ADCEN_I_SFT			1
#define NAU8310_ADCEN_I				(0x1 << NAU8310_ADCEN_I_SFT)
#define NAU8310_ADCEN_V_SFT			0
#define NAU8310_ADCEN_V				(0x1 << NAU8310_ADCEN_V_SFT)

/* INTERRUPT_CTRL (0x05) */
#define NAU8310_WD_INT_MASK_SFT			14
#define NAU8310_WD_INT_MASK			(0x1 << NAU8310_WD_INT_MASK_SFT)
#define NAU8310_DSP2I2C_INT_MASK_SFT		13
#define NAU8310_DSP2I2C_INT_MASK		(0x1 << NAU8310_DSP2I2C_INT_MASK_SFT)
#define NAU8310_ARP_DWN_INT_MASK_SFT		12
#define NAU8310_ARP_DWN_INT_MASK		(0x1 << NAU8310_ARP_DWN_INT_MASK_SFT)
#define NAU8310_CLIP_INT_MASK_SFT		11
#define NAU8310_CLIP_INT_MASK			(0x1 << NAU8310_CLIP_INT_MASK_SFT)
#define NAU8310_LVD_INT_MASK_SFT		10
#define NAU8310_LVD_INT_MASK			(0x1 << NAU8310_LVD_INT_MASK_SFT)
#define NAU8310_OVP_INT_MASK_SFT		9
#define NAU8310_OVP_INT_MASK			(0x1 << NAU8310_OVP_INT_MASK_SFT)
#define NAU8310_PWR_INT_DIS_SFT			8
#define NAU8310_PWR_INT_DIS			(0x1 << NAU8310_PWR_INT_DIS_SFT)
#define NAU8310_WD_INT_DIS_SFT			6
#define NAU8310_WD_INT_DIS			(0x1 << NAU8310_WD_INT_DIS_SFT)
#define NAU8310_DSP2I2C_INT_DIS_SFT		5
#define NAU8310_DSP2I2C_INT_DIS			(0x1 << NAU8310_DSP2I2C_INT_DIS_SFT)
#define NAU8310_ARP_DWN_INT_DIS_SFT		4
#define NAU8310_ARP_DWN_INT_DIS			(0x1 << NAU8310_ARP_DWN_INT_DIS_SFT)
#define NAU8310_CLIP_INT_DIS_SFT		3
#define NAU8310_CLIP_INT_DIS			(0x1 << NAU8310_CLIP_INT_DIS_SFT)
#define NAU8310_LVD_INT_DIS_SFT			2
#define NAU8310_LVD_INT_DIS			(0x1 << NAU8310_LVD_INT_DIS_SFT)
#define NAU8310_OVP_INT_DIS_SFT			1
#define NAU8310_OVP_INT_DIS			(0x1 << NAU8310_OVP_INT_DIS_SFT)
#define NAU8310_PWR_INT_MASK			0x1

/* INT_CLR_STATUS (0x06) */
#define NAU8310_INT_STATUS_MASK			0x7ff
#define NAU8310_INT_STATUS_WD			(0x1 << 6)
#define NAU8310_INT_STATUS_DSP2I2C		(0x1 << 5)
#define NAU8310_INT_STATUS_ARP_DWN		(0x1 << 4)
#define NAU8310_INT_STATUS_CLIP			(0x1 << 3)
#define NAU8310_INT_STATUS_LVD			(0x1 << 2)
#define NAU8310_INT_STATUS_OVP			(0x1 << 1)
#define NAU8310_INT_STATUS_PWR			0x1

/* SAR_CTRL1 (0x07) */
#define NAU8310_SAR_TRACKING_GAIN_SFT		11
#define NAU8310_SAR_TRACKING_GAIN_MASK		(0x7 << NAU8310_SAR_TRACKING_GAIN_SFT)
#define NAU8310_SAR_COMPARE_TIME_SFT		5
#define NAU8310_SAR_COMPARE_TIME_MASK		(0x3 << NAU8310_SAR_COMPARE_TIME_SFT)
#define NAU8310_SAR_SAMPLING_TIME_SFT		2
#define NAU8310_SAR_SAMPLING_TIME_MASK		(0x3 << NAU8310_SAR_SAMPLING_TIME_SFT)
#define NAU8310_SAR_ENA_SFT			0
#define NAU8310_SAR_ENA_EN			(0x1 << NAU8310_SAR_ENA_SFT)

/* IO_CTRL (0x0a) */
#define NAU8310_IRQ_PL_SFT			15
#define NAU8310_IRQ_PL_ACT_HIGH			(0x1 << NAU8310_IRQ_PL_SFT)
#define NAU8310_IRQ_DS_SFT			12
#define NAU8310_IRQ_DS_HIGH			(0x1 << NAU8310_IRQ_DS_SFT)
#define NAU8310_IRQ_OUTPUT_SFT			11
#define NAU8310_IRQ_OUTPUT_EN			(0x1 << NAU8310_IRQ_OUTPUT_SFT)
#define NAU8310_BCLK_DS_SFT			2
#define NAU8310_BCLK_DS_EN			(0x1 << NAU8310_BCLK_DS_SFT)
#define NAU8310_LRC_DS_SFT			1
#define NAU8310_LRC_DS_EN			(0x1 << NAU8310_LRC_DS_SFT)
#define NAU8310_ADCDAT_DS_SFT			0
#define NAU8310_ADCDAT_DS_EN			0x1

/* I2S_PCM_CTRL0 (0x0b) */
#define NAU8310_ALC_MODE_SFT			15
#define NAU8310_ALC_MODE			(0x1 << NAU8310_ALC_MODE_SFT)
#define NAU8310_ALC_SEND_ON_LOC_SFT		14
#define NAU8310_ALC_SEND_ON_LOC			(0x1 << NAU8310_ALC_SEND_ON_LOC_SFT)
#define NAU8310_DAC_SEL_SFT			10
#define NAU8310_DAC_SEL_MASK			(0x7 << NAU8310_DAC_SEL_SFT)
#define NAU8310_DAC_SEL_SLOT0			0
#define NAU8310_DAC_SEL_SLOT1			(0x1 << NAU8310_DAC_SEL_SFT)
#define NAU8310_DAC_SEL_SLOT2			(0x2 << NAU8310_DAC_SEL_SFT)
#define NAU8310_DAC_SEL_SLOT3			(0x3 << NAU8310_DAC_SEL_SFT)
#define NAU8310_DAC_SEL_SLOT4			(0x4 << NAU8310_DAC_SEL_SFT)
#define NAU8310_DAC_SEL_SLOT5			(0x5 << NAU8310_DAC_SEL_SFT)
#define NAU8310_DAC_SEL_SLOT6			(0x6 << NAU8310_DAC_SEL_SFT)
#define NAU8310_DAC_SEL_SLOT7			(0x7 << NAU8310_DAC_SEL_SFT)
#define NAU8310_AEC_CH_SEL_SFT			2
#define NAU8310_AEC_CH_SEL_RIGHT		(0x0 << NAU8310_AEC_CH_SEL_SFT)
#define NAU8310_AEC_CH_SEL_LEFT			(0x1 << NAU8310_AEC_CH_SEL_SFT)
#define NAU8310_AEC_SRC_SEL_SFT			1
#define NAU8310_AEC_SRC_SEL_DSP			(0x0 << NAU8310_AEC_SRC_SEL_SFT)
#define NAU8310_AEC_SRC_SEL_DAC			(0x1 << NAU8310_AEC_SRC_SEL_SFT)
#define NAU8310_AEC_MODE_SFT			0
#define NAU8310_AEC_MODE_IV			(0x0 << NAU8310_AEC_MODE_SFT)
#define NAU8310_AEC_MODE_AEC			(0x1 << NAU8310_AEC_MODE_SFT)

/* TDM_CTRL (0x0c) */
#define NAU8310_TDM_SFT				15
#define NAU8310_TDM_EN				(0x1 << NAU8310_TDM_SFT)
#define NAU8310_TDM_OFFSET_SFT			14
#define NAU8310_TDM_OFFSET_EN			(0x1 << NAU8310_TDM_OFFSET_SFT)
#define NAU8310_PINGPONG_SFT			13
#define NAU8310_PINGPONG_EN			(0x1 << NAU8310_PINGPONG_SFT)
#define NAU8310_ADC_ALC_SEL_SFT			6
#define NAU8310_ADC_ALC_SEL_MASK		(0xf << NAU8310_ADC_ALC_SEL_SFT)
#define NAU8310_ADC_I_SEL_SFT			3
#define NAU8310_ADC_I_SEL_MASK			(0x7 << NAU8310_ADC_I_SEL_SFT)
#define NAU8310_ADC_I_SEL_DIS			0
#define NAU8310_ADC_I_SEL_SLOT1			(0x4 << NAU8310_ADC_I_SEL_SFT)
#define NAU8310_ADC_I_SEL_SLOT3			(0x5 << NAU8310_ADC_I_SEL_SFT)
#define NAU8310_ADC_I_SEL_SLOT5			(0x6 << NAU8310_ADC_I_SEL_SFT)
#define NAU8310_ADC_I_SEL_SLOT7			(0x7 << NAU8310_ADC_I_SEL_SFT)
#define NAU8310_ADC_V_SEL_SFT			0
#define NAU8310_ADC_V_SEL_MASK			0x7
#define NAU8310_ADC_V_SEL_DIS			0
#define NAU8310_ADC_V_SEL_SLOT0			0x4
#define NAU8310_ADC_V_SEL_SLOT2			0x5
#define NAU8310_ADC_V_SEL_SLOT4			0x6
#define NAU8310_ADC_V_SEL_SLOT6			0x7

/* I2S_PCM_CTRL1 (0x0d) */
#define NAU8310_I2S_BP_SFT			7
#define NAU8310_I2S_BP_MASK			(0x1 << NAU8310_I2S_BP_SFT)
#define NAU8310_I2S_BP_INV			(0x1 << NAU8310_I2S_BP_SFT)
#define NAU8310_I2S_PCMB_SFT			6
#define NAU8310_I2S_PCMB_EN			(0x1 << NAU8310_I2S_PCMB_SFT)
#define NAU8310_I2S_DL_SFT			2
#define NAU8310_I2S_DL_MASK			(0x3 << NAU8310_I2S_DL_SFT)
#define NAU8310_I2S_DL_16			(0x0 << NAU8310_I2S_DL_SFT)
#define NAU8310_I2S_DL_20			(0x1 << NAU8310_I2S_DL_SFT)
#define NAU8310_I2S_DL_24			(0x2 << NAU8310_I2S_DL_SFT)
#define NAU8310_I2S_DL_32			(0x3 << NAU8310_I2S_DL_SFT)
#define NAU8310_I2S_DF_MASK			0x3
#define NAU8310_I2S_DF_RIGHT			0x0
#define NAU8310_I2S_DF_LEFT			0x1
#define NAU8310_I2S_DF_I2S			0x2
#define NAU8310_I2S_DF_PCM_AB			0x3

/* I2S_PCM_CTRL2 (0x0e) */
#define NAU8310_I2S_TRISTATE_SFT		15
#define NAU8310_I2S_TRISTATE			(1 << NAU8310_I2S_TRISTATE_SFT)
#define NAU8310_I2S_LRC_DIV_SFT			12
#define NAU8310_I2S_LRC_DIV_MASK		(0x3 << NAU8310_I2S_LRC_DIV_SFT)
#define NAU8310_I2S_ADCDAT_OE_SFT		4
#define NAU8310_I2S_ADCDAT_OE_MASK		(1 << NAU8310_I2S_ADCDAT_OE_SFT)
#define NAU8310_I2S_ADCDAT_OE_EN		(0 << NAU8310_I2S_ADCDAT_OE_SFT)
#define NAU8310_I2S_ADCDAT_OE_DIS		(1 << NAU8310_I2S_ADCDAT_OE_SFT)
#define NAU8310_I2S_MS_SFT			3
#define NAU8310_I2S_MS_MASK			(0x1 << NAU8310_I2S_MS_SFT)
#define NAU8310_I2S_MS_MASTER			(0x1 << NAU8310_I2S_MS_SFT)
#define NAU8310_I2S_BLK_DIV_MASK		0x7

/* MUTE_CTRL (0x13) */
#define NAU8310_SOFT_MUTE_SFT			15
#define NAU8310_SOFT_MUTE			(0x1 << NAU8310_SOFT_MUTE_SFT)
#define NAU8310_DAC_ZE_SFT			8
#define NAU8310_DAC_ZE_EN			(0x1 << NAU8310_DAC_ZE_SFT)
#define NAU8310_DAC_VOL_SFT			0
#define NAU8310_DAC_VOL_MAX			0xff

/* ADC_VOL_CTRL (0x14) */
#define NAU8310_ADC_GAIN_L_SFT			8
#define NAU8310_ADC_GAIN_L_MAX			0xc1
#define NAU8310_ADC_GAIN_L_MASK			(0xff << NAU8310_ADC_GAIN_L_SFT)
#define NAU8310_ADC_GAIN_R_SFT			0
#define NAU8310_ADC_GAIN_R_MAX			0xc1
#define NAU8310_ADC_GAIN_R_MASK			0xff

/* BOOST_CTRL1 (0x17) */
#define NAU8310_BSTLIMIT_SFT			8
#define NAU8310_BSTLIMIT_MAX			0x3f
#define NAU8310_BSTLIMIT_MASK			(0x3f << NAU8310_BSTLIMIT_SFT)
#define NAU8310_BSTMARGIN_SFT			0
#define NAU8310_BSTMARGIN_MAX			0x3f
#define NAU8310_BSTMARGIN_MASK			0x3f

/* BOOST_CTRL2 (0x18) */
#define NAU8310_TC_SFT				15
#define NAU8310_TC_EN				(0x1 << NAU8310_TC_SFT)
#define NAU8310_BSTHOLD_SFT			7
#define NAU8310_BSTHOLD_MASK			(0xf << NAU8310_BSTHOLD_SFT)
#define NAU8310_BSTSTEPTIME_SFT			4
#define NAU8310_BSTSTEPTIME_MASK		(0x7 << NAU8310_BSTSTEPTIME_SFT)
#define NAU8310_BSTDELAY_MASK			0xf

/* DSP_CORE_CTRL2 (0x1a) */
#define NAU8310_DAC_SEL_DSP_SFT			5
#define NAU8310_DAC_SEL_DSP_OUT			(0x1 << NAU8310_DAC_SEL_DSP_SFT)
#define NAU8310_DSP_RUNSTALL_SFT		4
#define NAU8310_DSP_RUNSTALL			(0x1 << NAU8310_DSP_RUNSTALL_SFT)

/* ADC_RATE (0x28) */
#define NAU8310_I2S_MODE_SFT			15
#define NAU8310_I2S_MODE			(0x1 << NAU8310_I2S_MODE_SFT)
#define NAU8310_UNSIGN_IV_SFT			8
#define NAU8310_UNSIGN_IV			(0x1 << NAU8310_UNSIGN_IV_SFT)
#define NAU8310_ADC_SYNC_DOWN_SFT		0
#define NAU8310_ADC_SYNC_DOWN_MASK		0x3
#define NAU8310_ADC_SYNC_DOWN_32		0
#define NAU8310_ADC_SYNC_DOWN_64		1
#define NAU8310_ADC_SYNC_DOWN_128		2

/* DAC_CTRL1 (0x29) */
#define NAU8310_DAC_OVERSAMPLE_SFT		0
#define NAU8310_DAC_OVERSAMPLE_MASK		0x7
#define NAU8310_DAC_OVERSAMPLE_64		0
#define NAU8310_DAC_OVERSAMPLE_256		1
#define NAU8310_DAC_OVERSAMPLE_128		2
#define NAU8310_DAC_OVERSAMPLE_32		4

/* ALC_CTRL1 (0x2c) */
#define NAU8310_ALC_MAXGAIN_SFT			5
#define NAU8310_ALC_MAXGAIN_MAX			0x7
#define NAU8310_ALC_MAXGAIN_MASK		(0x7 << NAU8310_ALC_MAXGAIN_SFT)
#define NAU8310_ALC_MINGAIN_SFT			1
#define NAU8310_ALC_MINGAIN_MAX			4
#define NAU8310_ALC_MINGAIN_MASK		(0x7 << NAU8310_ALC_MINGAIN_SFT)
#define NAU8310_ALC_GAIN_SEL_SFT		0
#define NAU8310_ALC_GAIN_SEL_MODE		1

/* ALC_CTRL2 (0x2d) */
#define NAU8310_ALC_DCY_SFT			12
#define NAU8310_ALC_DCY_MAX			0xb
#define NAU8310_ALC_DCY_MASK			(0xf << NAU8310_ALC_DCY_SFT)
#define NAU8310_ALC_ATK_SFT			8
#define NAU8310_ALC_ATK_MAX			0xb
#define NAU8310_ALC_ATK_MASK			(0xf << NAU8310_ALC_ATK_SFT)
#define NAU8310_ALC_HLD_SFT			4
#define NAU8310_ALC_HLD_MAX			0xa
#define NAU8310_ALC_HLD_MASK			(0xf << NAU8310_ALC_HLD_SFT)
#define NAU8310_ALC_LVL_SFT			0
#define NAU8310_ALC_LVL_MAX			0xf
#define NAU8310_ALC_LVL_MASK			0xf

/* ALC_CTRL3 (0x2e) */
#define NAU8310_ALC_EN_SFT			15
#define NAU8310_ALC_EN				(0x1 << NAU8310_ALC_EN_SFT)
#define NAU8310_LIM_MDE_SFT			12
#define NAU8310_LIM_MDE_MASK			(0x7 << NAU8310_LIM_MDE_SFT)
#define NAU8310_VBAT_THLD_SFT			5
#define NAU8310_VBAT_THLD_MAX			0x1f
#define NAU8310_VBAT_THLD_MASK			(0x1f << NAU8310_VBAT_THLD_SFT)
#define NAU8310_AUTOATT_EN_SFT			4
#define NAU8310_AUTOATT_EN			(0x1 << NAU8310_AUTOATT_EN_SFT)

/* TEMP_COMP_CTRL (0x30) */
#define NAU8310_TEMP_COMP_ACT2_MASK		0xff

/* LPF_CTRL (0x33) */
#define NAU8310_LPF_IN1_EN_SFT			15
#define NAU8310_LPF_IN1_EN			(0x1 << NAU8310_LPF_IN1_EN_SFT)
#define NAU8310_LPF_IN1_TC_SFT			11
#define NAU8310_LPF_IN1_TC_MASK			(0xf << NAU8310_LPF_IN1_TC_SFT)
#define NAU8310_LPF_IN2_EN_SFT			10
#define NAU8310_LPF_IN2_EN			(0x1 << NAU8310_LPF_IN2_EN_SFT)
#define NAU8310_LPF_IN2_TC_SFT			6
#define NAU8310_LPF_IN2_TC_MASK			(0xf << NAU8310_LPF_IN2_TC_SFT)

/* CLK_DET_CTRL (0x40) */
#define NAU8310_APWRUP_SFT			15
#define NAU8310_APWRUP_EN			(0x1 << NAU8310_APWRUP_SFT)
#define NAU8310_CLKPWRUP_SFT			14
#define NAU8310_CLKPWRUP_DIS			(0x1 << NAU8310_CLKPWRUP_SFT)
#define NAU8310_PWRUP_DFT_SFT			13
#define NAU8310_PWRUP_DFT			(0x1 << NAU8310_PWRUP_DFT_SFT)
#define NAU8310_SRATE_SFT			10
#define NAU8310_SRATE_MASK			(0x7 << NAU8310_SRATE_SFT)
#define NAU8310_ALT_SRATE_SFT			9
#define NAU8310_ALT_SRATE_EN			(0x1 << NAU8310_ALT_SRATE_SFT)
#define NAU8310_DIV_MAX				0x1

/* I2C_DEVICE_ID (0x46) */
#define NAU8310_I2C_DEVICE_ID_SFT		8
#define NAU8310_I2C_DEVICE_ID_MASK		(0x7f << NAU8310_I2C_DEVICE_ID_SFT)
#define NAU8310_REG_SI_REV_MASK			0xff
#define NAU8310_REG_SI_REV_G10			0xe1
#define NAU8310_REG_SI_REV_G20			0x61

/* BIAS_ADJ (0x60) */
#define NAU8310_BIAS_VMID_SEL_SFT		4
#define NAU8310_BIAS_VMID_SEL_MASK		(0x3 << NAU8310_BIAS_VMID_SEL_SFT)

/* ANALOG_CONTROL_1 (0x61) */
#define NAU8310_ISEN_SFT			14
#define NAU8310_ISEN_MASK			(0x3 << NAU8310_ISEN_SFT)
#define NAU8310_ADCRSTEN_SFT			12
#define NAU8310_ADCRSTEN_MASK			(0x3 << NAU8310_ADCRSTEN_SFT)
#define NAU8310_VSEN_SFT			10
#define NAU8310_VSEN_MASK			(0x3 << NAU8310_VSEN_SFT)
#define NAU8310_ADCEN_SFT			8
#define NAU8310_ADCEN_MASK			(0x3 << NAU8310_ADCEN_SFT)
#define NAU8310_DACCLKEN_SFT			6
#define NAU8310_DACCLKEN_MASK			(0x3 << NAU8310_DACCLKEN_SFT)
#define NAU8310_DACEN_SFT			4
#define NAU8310_DACEN_MASK			(0x3 << NAU8310_DACEN_SFT)
#define NAU8310_BIASEN_SFT			2
#define NAU8310_BIASEN_MASK			(0x3 << NAU8310_BIASEN_SFT)
#define NAU8310_VMIDEN_MASK			0x3

/* ANALOG_CONTROL_2 (0x62) */
#define NAU8310_CLASSDEN_SFT			4
#define NAU8310_CLASSDEN_MASK			(0x3 << NAU8310_CLASSDEN_SFT)
#define NAU8310_PDVMDFST_SFT			2
#define NAU8310_PDVMDFST_MASK			(0x3 << NAU8310_PDVMDFST_SFT)
#define NAU8310_BSTEN_MASK			0x3

/* ANALOG_CONTROL_3 (0x63) */
#define NAU8310_DACREFCAP_SFT			4
#define NAU8310_DACREFCAP_MASK			(0x3 << NAU8310_DACREFCAP_SFT)

/* ANALOG_CONTROL_4 (0x64) */
#define NAU8310_RECV_MODE_SFT			15
#define NAU8310_RECV_MODE			(0x1 << NAU8310_RECV_MODE_SFT)
#define NAU8310_AUTOATTMIN_SFT			14
#define NAU8310_AUTOATTMIN_MASK			(0x1 << NAU8310_AUTOATTMIN_SFT)
#define NAU8310_AUTOATTMIN_12DB			(0x0 << NAU8310_AUTOATTMIN_SFT)
#define NAU8310_AUTOATTMIN_0DB			(0x1 << NAU8310_AUTOATTMIN_SFT)
#define NAU8310_CLASSD_SHORTP_SFT		10
#define NAU8310_CLASSD_SHORTP_MASK		(0xf << NAU8310_CLASSD_SHORTP_SFT)
#define NAU8310_CLASSD_SHORTP_NOMINAL		(0x0 << NAU8310_CLASSD_SHORTP_SFT)
#define NAU8310_CLASSD_SHORTP_33UP		(0x1 << NAU8310_CLASSD_SHORTP_SFT)
#define NAU8310_CLASSD_SHORTP_100UP		(0x3 << NAU8310_CLASSD_SHORTP_SFT)
#define NAU8310_CLASSD_SHORTP_22DOWN		(0x8 << NAU8310_CLASSD_SHORTP_SFT)
#define NAU8310_CLASSD_SHORTP_33DOWN		(0xc << NAU8310_CLASSD_SHORTP_SFT)
#define NAU8310_CLASSD_SHORTN_SFT		6
#define NAU8310_CLASSD_SHORTN_MASK		(0xf << NAU8310_CLASSD_SHORTN_SFT)
#define NAU8310_CLASSD_SHORTN_NOMINAL		(0x0 << NAU8310_CLASSD_SHORTN_SFT)
#define NAU8310_CLASSD_SHORTN_33UP		(0x1 << NAU8310_CLASSD_SHORTN_SFT)
#define NAU8310_CLASSD_SHORTN_100UP		(0x3 << NAU8310_CLASSD_SHORTN_SFT)
#define NAU8310_CLASSD_SHORTN_22DOWN		(0x8 << NAU8310_CLASSD_SHORTN_SFT)
#define NAU8310_CLASSD_SHORTN_33DOWN		(0xc << NAU8310_CLASSD_SHORTN_SFT)
#define NAU8310_CLASSD_SLEWP_SFT		3
#define NAU8310_CLASSD_SLEWP_MASK		(0x7 << NAU8310_CLASSD_SLEWP_SFT)
#define NAU8310_CLASSD_SLEWP_NOMINAL		(0x0 << NAU8310_CLASSD_SLEWP_SFT)
#define NAU8310_CLASSD_SLEWP_25UP		(0x1 << NAU8310_CLASSD_SLEWP_SFT)
#define NAU8310_CLASSD_SLEWP_50UP		(0x2 << NAU8310_CLASSD_SLEWP_SFT)
#define NAU8310_CLASSD_SLEWP_75UP		(0x3 << NAU8310_CLASSD_SLEWP_SFT)
#define NAU8310_CLASSD_SLEWP_OFF		(0x4 << NAU8310_CLASSD_SLEWP_SFT)
#define NAU8310_CLASSD_SLEWP_75DOWN		(0x5 << NAU8310_CLASSD_SLEWP_SFT)
#define NAU8310_CLASSD_SLEWP_50DOWN		(0x6 << NAU8310_CLASSD_SLEWP_SFT)
#define NAU8310_CLASSD_SLEWP_25DOWN		(0x7 << NAU8310_CLASSD_SLEWP_SFT)
#define NAU8310_CLASSD_SLEWN_SFT		0
#define NAU8310_CLASSD_SLEWN_MASK		0x7
#define NAU8310_CLASSD_SLEWN_NOMINAL		0x0
#define NAU8310_CLASSD_SLEWN_25UP		0x1
#define NAU8310_CLASSD_SLEWN_50UP		0x2
#define NAU8310_CLASSD_SLEWN_75UP		0x3
#define NAU8310_CLASSD_SLEWN_OFF		0x4
#define NAU8310_CLASSD_SLEWN_75DOWN		0x5
#define NAU8310_CLASSD_SLEWN_50DOWN		0x6
#define NAU8310_CLASSD_SLEWN_25DOWN		0x7

/* ANALOG_CONTROL_5 (0x65) */
#define NAU8310_BSTINDR_SFT			12
#define NAU8310_BSTINDR_MASK			(0x7 << NAU8310_BSTINDR_SFT)
#define NAU8310_BSTCURGEN_SFT			8
#define NAU8310_BSTCURGEN_MASK			(0xf << NAU8310_BSTCURGEN_SFT)
#define NAU8310_BSTMONEN_SFT			7
#define NAU8310_BSTMONEN			(0x1 << NAU8310_BSTMONEN_SFT)
#define NAU8310_BSTNOVPN_SFT			3
#define NAU8310_BSTNOVPN_MASK			(0x3 << NAU8310_BSTNOVPN_SFT)
#define NAU8310_BSTCLKPULSE_MASK		0x3

/* ANALOG_CONTROL_6 (0x66) */
#define NAU8310_BSTRADJ_SFT			12
#define NAU8310_BSTRADJ_MASK			(0x7 << NAU8310_BSTRADJ_SFT)
#define NAU8310_BSTSLEWPOFF_SFT			10
#define NAU8310_BSTSLEWPOFF_MASK		(0x3 << NAU8310_BSTSLEWPOFF_SFT)
#define NAU8310_BSTSLEWPON_SFT			8
#define NAU8310_BSTSLEWPON_MASK			(0x3 << NAU8310_BSTSLEWPON_SFT)
#define NAU8310_BSTSLEWNON_SFT			6
#define NAU8310_BSTSLEWNON_MASK			(0x3 << NAU8310_BSTSLEWNON_SFT)
#define NAU8310_BSTSLEWNOFF_SFT			4
#define NAU8310_BSTSLEWNOFF_MASK		(0x3 << NAU8310_BSTSLEWNOFF_SFT)
#define NAU8310_BSTIPDR_MASK			0x7

/* ANALOG_CONTROL_7 (0x68) */
#define NAU8310_ADCGAIN_SFT			9
#define NAU8310_ADCGAIN_MASK			(0x3 << NAU8310_ADCGAIN_SFT)
#define NAU8310_VREFBG_SFT			6
#define NAU8310_VREFBG_EN			(0x1 << NAU8310_VREFBG_SFT)
#define NAU8310_MU_HALF_RANGE_SFT		3
#define NAU8310_MU_HALF_RANGE_EN		(0x1 << NAU8310_MU_HALF_RANGE_SFT)
#define NAU8310_MCLKX_MASK			0x7
#define NAU8310_MCLK16XEN			0x4
#define NAU8310_MCLK8XEN			0x2
#define NAU8310_MCLK4XEN			0x1

/* ANALOG_CONTROL_8 (0x6b) */
#define NAU8310_VBAT_PCL_SFT			11
#define NAU8310_VBAT_PCL_MAX			0x1f
#define NAU8310_VBAT_PCL_MASK			(0x1f << NAU8310_VBAT_PCL_SFT)
#define NAU8310_VBAT_THD_SFT			4
#define NAU8310_VBAT_THD_MAX			0xf
#define NAU8310_VBAT_THD_MASK			(0xf << NAU8310_VBAT_THD_SFT)

/* ANALOG_CONTROL_9 (0x6c) */
#define NAU8310_VBAT_CURLMT_MASK		0x1f

/* RDAC (0x73) */
#define NAU8310_DACVREFSEL_SFT			2
#define NAU8310_DACVREFSEL_MASK			(0x3 << NAU8310_DACVREFSEL_SFT)

/* BOOST (0x76) */
#define NAU8310_STG2_SEL_SFT			14
#define NAU8310_STG2_SEL_CLASSA			(0x1 << NAU8310_STG2_SEL_SFT)

/* FEPGA (0x77) */
#define NAU8310_CURR_TRIM_SFT			8
#define NAU8310_CURR_TRIM_MAX			0x7
#define NAU8310_CURR_TRIM_MASK			(0x7 << NAU8310_CURR_TRIM_SFT)
#define NAU8310_CMLCK_ENB_SFT			7
#define NAU8310_CMLCK_ENB			(0x1 << NAU8310_CMLCK_ENB_SFT)

/* POWER_UP_CONTROL (0x7f) */
#define NAU8310_PGA_GAIN_SFT			4
#define NAU8310_PGA_GAIN_MAX			0x4
#define NAU8310_PGA_GAIN_MASK			(0x7 << NAU8310_PGA_GAIN_SFT)


#define NAU8310_CODEC_DAI "nau8310-hifi"


struct nau8310 {
	struct device *dev;
	struct regmap *regmap;
	struct snd_soc_dapm_context *dapm;
	char silicon_id;
	int irq;
	int mclk;
	int fs;
	int vref_impedance;
	int dac_vref;
	int sar_voltage;
	int sar_compare_time;
	int sar_sampling_time;
	int clock_detection;
	int clock_det_data;
	int temp_compensation;
	int boost_delay;
	int boost_convert_enable;
	int boost_target_limit;
	int boost_target_margin;
	int normal_iis_data;
	int alc_enable;
	int aec_enable;
	/* DSP data */
	int dsp_enable;
	int kcs_setup_size;
};

struct nau8310_src_attr {
	int param;
	unsigned int val;
};

enum {
	NAU8310_MCLK_FS_RATIO_256,
	NAU8310_MCLK_FS_RATIO_400,
	NAU8310_MCLK_FS_RATIO_500,
	NAU8310_MCLK_FS_RATIO_NUM,
};

struct nau8310_srate_attr {
	int fs;
	int range;
	bool max;
	unsigned int mclk_src[NAU8310_MCLK_FS_RATIO_NUM];
	int adc_div;
};

struct nau8310_osr_attr {
	unsigned int osr;
	unsigned int clk_src;
};

int nau8310_enable_dsp(struct snd_soc_codec *codec);

#endif /* __NAU8310_H__ */
